FPGA Implementation and Analysis of a Three-Digit Seven-Segment Slot Machine System

 

This paper presents a complete FPGA-based implementation and engineering analysis of a three-reel digital slot machine using Verilog HDL. The design integrates a deterministic timing generator, three independent reel controllers, and a time-division multiplexed (TDM) seven-segment display driver. The system utilizes a 50\,MHz reference clock, internally divided to produce a visible reel-increment rate of approximately 12\,Hz. A multiplexed display architecture reduces I/O usage by driving three digits with a single 8-bit segment bus and four digit-enable lines. Detailed analysis of clock division, finite-state reel logic, seven-segment decoding, and TDM display refresh is provided. The FPGA pin assignments are tabulated, and the final design is validated through behavioral analysis and architectural diagrams.

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